Senior Staff Engineer SOC Implementation

About the role

As a Senior Staff Engineer SOC Implementation you will join Infineon’s Research & Development team to lead the physical implementation of complex digital SoC designs. You will combine creativity with deep technical expertise to shape next‑generation semiconductor solutions.

Key responsibilities

• Implement and integrate complex digital SoC designs, focusing on floorplanning, placement, clock‑tree synthesis, routing and power distribution.
• Translate high‑level specifications into detailed layout using state‑of‑the‑art EDA tools to achieve timing closure, signal integrity and physical sign‑off.
• Drive the RTL‑to‑GDS flow independently, covering synthesis, equivalence checking and physical implementation.
• Develop innovative clocking architectures for deep‑sub‑micron FINFET technologies and collaborate with cross‑functional teams.
• Participate in expert networks to advance methodology and flow topics in SoC floorplanning and top‑level timing closure.

Required profile

• Degree in Electrical Engineering, Microelectronics or related field.
• 5+ years of experience in physical design of highly complex SoCs, including synthesis, place & route and timing closure.
• Proven technical leadership on physical‑design projects.
• Fluent English; German is a plus.

Required skills

• Synopsys and Cadence EDA toolsets (RTL2GDS flow).
• Scripting in Tcl, Perl or Python.
• RTL coding basics.
• Knowledge of FINFET technologies and functional safety concepts.