Formal Verification Engineer

About the role

We are looking for an early‑career Formal Verification Engineer to join our team and develop expertise in formal methods. You will work side‑by‑side with senior engineers on customer projects, learning our LUBIS methodology and gradually taking ownership of formal verification deliverables.

Key responsibilities

• Read specifications and RTL, clarify intent with design teams.
• Implement SystemVerilog Assertions (SVA) and run formal proofs using JasperGold, Questa Formal or VC Formal.
• Debug counter‑examples, document findings and close the loop with senior engineers.
• Maintain clean, reviewable work artifacts – assumptions, evidence and results.
• Participate in testing new releases of verification tools and provide feedback.

Required profile

• First‑hand experience with formal verification or a strong foundation in digital verification/design.
• Solid SystemVerilog knowledge and enthusiasm to deepen SVA skills.
• Structured thinker who enjoys debugging and solving puzzles.
• Proactive attitude – able to own small, well‑scoped tasks with senior support.

Required skills

• JasperGold
• Questa Formal
• VC Formal
• SystemVerilog
• SVA (SystemVerilog Assertions)
• RTL design understanding

What we offer

• On‑site work at least 50 % of the time with a supportive team.
• Structured onboarding bootcamp, paired projects and regular review cycles.
• Clear career path toward a Professional Formal Verification Engineer role within 12‑18 months.